1. Cross-Reference to Related Application
U.S. patent application Ser. No. 448,135 entitled "True/Complement Generator", filed Dec. 9, 1982 by M. Grandguillot et al and of common assignee herewith.
2. Field of the Invention
The invention relates to a phase splitter with an integrated latch circuit. complement generator connected via a first clock-controlled switch to a current supply, and supplying complementary output signals as a function of an input signal, and having connected at its outputs one respective output stage.
3. Description of Prior Art
In its most conventional form, phase splitters consist of an inverter which supplies the inverted value of the input signal, whereas the non-inverted value is supplied through a direct connection of the input with the corresponding output. The numerous published and patented variations of this basic form show that for solving new problems a great variety of improvements and developments are required. So the mere generation of the inverted or complementary, and of the non-inverted or true output signal (which corresponds to the generation of an in-phase and of an out-of-phase signal) out of a given input signal is frequently not sufficient for ensuring the desired qualitative characteristics of the phase splitter. The demands for increased speed, reduced power dissipation, and exact timing between the individual signals in the circuit frequently necessitate the development of improved circuits and modes of operation. If the circuits are made in integrated technology there is the added demand for the realization of the circuit in a semiconductor body involving a minimum of space.
Many bistable circuits, e.g. in the form of flip-flops are also known and widely used. They also include latch circuits. The mode of operation of such circuits is an input receives a set signal and at the output an in-phase, or out-of-phase output, signal is generated. Owing to the feedback or latch function this output signal remains, even if in the meantime the set signal has been switched off. The output signal, i.e. the switching state of the circuit is maintained until a reset signal is applied to a reset input. In the known circuits of this kind the output signal is always delayed relative to the input signal releasing the switching process. The extent of this switching delay depends on the duration of the latching or switching process of the circuit itself. In high speed circuits of this kind, these time delays are frequently undesired or even inadmissible.
The following U.S. patents and publications are merely cited as background information. At least certain ones thereof are briefly discussed hereinafter. Further, the patents and publications listed below are not necessarily the most pertinent prior art.
U.S. Pat. No. 3,764,823 entitled "Timed True and Complement Generator" granted Oct. 9, 1973 to N. M. Donofrio et al. PA1 U.S. Pat. No. 3,846,643 entitled "Delayless Transistor Latch Circuit" granted Nov. 5, 1974 to W. M. Chu et al. PA1 U.S. Pat. No. 4,053,873 entitled "Self-Isolating Cross-Coupled Sense Amplifier Latch Circuit" granted Oct. 11, 1977 to L. B. Freeman et al. PA1 "Address Buffer True/Complement Generator" by A. Furman, IBM Technical Disclosure Bulletin, Vol. 18, No. 11, April 1976, pp. 3597-8. PA1 "Latched Inverter Buffer Circuit" by H. O. Askin et al, IBM Technical Disclosure Bulletin, Vol. 20, No. 4, September 1977, p. 1426-9. PA1 "Data-Out Path with Minimum Delay" by H. H. Heimeier et al, IBM Technical Disclosure Bulletin, Vol. 24, No. 1B, June 1981, pp. 534-5.
From German Auslegeschrift No. 24 22 123, (U.S. Pat. No. 3,846,643) to give an example, a bistable latch circuit is known where the time delay of the output signal relative to the releasing input signal is reduced. An input-output circuit is provided which after an input signal directly supplies an output signal. The input-output circuit is coupled to the latch circuit which latches after the input signal, and thus maintains the output signal. The disadvantage of this circuit is that the latch circuit is in continuous operation and consequently continuously power-consuming, and has to be switched together with the input signal. This switching is a load on the input-output circuit and again causes an undesired time delay.
Quite a number of uses for a phase splitter are known where it is composed of a true-complement generator and a latch circuit. The purpose of this combination is to obtain through an input signal out-of-phase output signals in a minimum of time, and subsequently to effect a latching so that the set switching state is maintained even if the input signal is switched off, or even if there is a subsequent adding of a second input signal complementary to the first one.
Important fields of use are latching buffer circuits and latching read circuits for semiconductor storages. Buffer circuits are published e.g. in "IBM Technical Disclosure Bulletin", Vol. 20, No. 4, September 1977, pp. 1426-1429 and in "IBM Technical Disclosure Bulletin", Vol. 18, No. 11, April 1976, pp. 3597 and 3598. Apart from a true-complement generator, these circuits comprise a latch circuit where the signals supplied by the true-complement generator remain stored also after the releasing input signal of the true-complement generator, and are kept ready for further use. A disadvantage of the circuit of the first mentioned publication is that the output signal is available only after determination of the latching process, and that complex clocking of the circuit is required. Also, in the circuit disclosed in the second publication cited above, delays are caused in that the output signals are influenced by the latching process since the latching circuit is connected in parallel to the outputs of the true-complement generator.
Similar disadvantages are also shown by the latch read amplifiers disclosed in "IBM Technical Disclosure Bulletin, Vol. 20, No. 1B, June 1981, pp. 534 and 535, and in German Offenlegungsschrift No. 27 21 851 (U.S. Pat. No. 4,053,873). Here, too, it is a disadvantage that the latches used in the form of flip-flops are continuously active, i.e. that they are continuously current-conducting and can be switched in a corresponding switching process from one state into the other, thus causing additional delays.